The present invention relates to a computer system which has a power save mode for reducing power dissipation suitable for, for instance, a laptop or notebook personal computer and a method of controlling power saving in a cache memory used with the computer system.
In recent years, various notebook computers which are easy to carry and can run on batteries have been developed. To reduce wasteful power dissipation, computers of this type have various power saving functions built in.
Typical power saving functions include CPU sleep mode functions of automatically stopping the CPU at the time the system is idle, suspend functions of not only stopping the CPU but turning off power to substantially all devices except the system memory of the computer system, and functions of stopping the hard disk driving motor or turning off the display under predetermined conditions.
Recently, for improved system performance, many desktop computers have begun to adopt a secondary cache consisting of a fast SRAM or the like. With a system having a secondary cache built in, the CPU wait time due to a relatively long memory cycle for access to the main storage is saved, permitting the CPU performance to be displayed fully. As a type of fast SRAM suitable for use as the secondary cache, a pipeline burst SRAM (PBSRAM) is known. With the PBSRAM, the burst transfer cycle between the CPU and the secondary cache can be made considerably faster than with the normal asynchronous fast SRAM.
However, the conventional suspend and CPU sleep functions are not provided with means for attaining power saving of the secondary cache. For this reason, the incorporation of a secondary cache into a notebook personal computer requiring low power dissipation improves the operating speed but reduces the time the computer can operate on a battery. In the suspend mode, not only the system memory but also the secondary cache requires battery voltage to hold stored data. Thus, the time that data can be held is also reduced, which significantly affects a fast SRAM, such as a PBSRAM in particular, because it has large power dissipation.
PBSRAMs which have been developed recently include ones of a type with a low power dissipation mode (for instance, the Toshiba TC55V1325). This type of PBSRAM has a power-down input terminal referred to as a ZZ pin. When a power-down signal applied to the input terminal becomes active, the mode of operation is switched from the normal operation mode to the low power dissipation mode. In the low power dissipation mode, all input signals including a clock signal are blocked. The current dissipation can be suppressed to as much as 2 mA even with a clock applied. Data is held during the low power dissipation mode. When the power-down signal goes inactive, the operation mode is switched from the low power dissipation mode back to the normal operation mode. Even if the switching is made to the normal operation mode, the PBSRAM cannot operate immediately: it is necessary to wait about 100 ns from when the operation mode is switched until the normal operation is ensured.
In using a PBSRAM having the ZZ pin as a secondary cache, therefore, it is required to make the secondary cache unavailable for a fixed period after the operation mode is switched back to the normal operation mode. This is intended to prevent malfunctions due to access to the secondary cache made by the CPU during an interval in which the normal operation of the PBSRAM is not ensured.
While the CPU is operating in the normal mode, not the above-mentioned sleep mode or suspend mode, no measures are taken to save power in the secondary cache memory. It is desired that some measures be taken to save power in the secondary cache memory while the CPU is operating in the normal mode, not only in a desk-top personal computer but also in a portable personal computer in which power should be saved as much as possible.